To avoid leakage between devices and latchup problems within a device, it is necessary to provide electrical isolation both between and within devices. For many years this was accomplished by means of LOCOS (Local Oxidation of Silicon). In this process, thick layers of oxide were grown on the silicon surface in selected areas. These oxide layers extended both below as well as above the silicon surface and had a relatively gentle slope where they met the silicon surface. This sloped interface limited the device densities that could be achieved in an integrated circuit.
Significant improvement in device densities can be achieved if LOCOS is replaced by STI (shallow trench isolation). In the latter process, trenches having relatively steep sidewalls are first etched into the silicon and are then filled with dielectric, usually silicon oxide deposited by CVD (chemical vapor deposition). Since the top surface of the filler material is co-planar with the silicon surface, formation of fine wiring running across both surfaces does not present any problems.
To understand the problem that is addressed by the present invention we refer now to FIG. 1. Shown there are a pair of trenches, in silicon body 11, that have been over-filled with dielectric material (silicon oxide) 12. Lining the walls of the trenches is layer 13 of thermal oxide which has been included to remove defects resulting from the trench etch. Over-filling is necessary to guarantee that inadvertent under-filling does not occur and also to provide a passivation layer for the silicon side wall.
During the removal of the silicon nitride as well as in subsequent process steps such as HF cleaning, spacer etching, etc., as illustrated in FIG. 2, grooves such as 29 are formed at the interface between the filler dielectric 112 and the silicon 11. As the sidewalls of the trenches become steeper (in order to achieve greater device densities), this problem becomes more common. In many cases (particularly when the sidewalls depart from the vertical by less than about 78 degrees) such grooves may be deep enough to expose the PN junction between source/drain regions 25 and the main silicon body 11. Said junctions were formed as part of a self-aligned LDD (lightly doped drain) process in which polysilicon gate 21, over gate oxide layer 22, served as its own mask during ion implantation. The latter process was performed in two steps, once before and once after the formation of spacers 23 on the sidewalls of 21, giving regions 25 their characteristic stepped appearance.
Of itself, the exposure of the junction is not a serious problem. However, once the structure shown in FIG. 2 has been formed, the next step in the process is to make separate, non touching, contacts to the gate pedestal and to the source/drain regions. This is most widely accomplished by means of the SALICIDE (self-aligned silicide) process in which a layer of a silicide forming metal, such as cobalt, is deposited over the entire structure and then briefly heated. Wherever the metal is in direct contact with silicon, the silicide is formed and the metal remains unreacted elsewhere. A selective etch then removes all unreacted metal, leaving the silicide (which is a good conductor) in place as a contacting medium where needed and absent where it is not wanted. In particular, it is not present over the spacers 23.
The consequences of exposing an edge of the source/drain junction are illustrated in FIG. 3 which is an enlarged view of the portion of FIG. 2 enclosed in the broken circle. Silicide layer 36 is seen to have been grown on the upper surface of 25, as intended. However, because of the exposure, in groove 29, of the surface at the edge of the junction between 25 and 11, silicide has grown there too. This represents a serious problem since layer 36 now acts to short circuit the PN junction. The present invention is dedicated to solving this problem.
A routine search of the patent literature was conducted but no references that approach the problem in the manner taught by the present invention were found. Several references of interest were, however, encountered. For example, Tsai et al. (U.S. Pat. No. 5,821,153) describe a similar problem, namely the presence of a gap at the edge of field oxide formed by LOCOS. They solve this problem by growing a protective coating of silicon oxynitride around the field oxide. In Duane (U.S. Pat. No. 5,686,346), nitride over oxide is described as a means for reducing the natural encroachment of field oxide into the active area. The patent teaches removal of this additional layer of nitride after devices have been formed.
Roberts (U.S. Pat. No. 5,118,641) also limits the total encroachment of field oxide. He deliberately makes the FOX too small, leaving some of the silicon exposed, then protects this exposed silicon with silicon nitride. The silicon nitride does not cover any exposed P-N junctions in this method. Liaw et al. (U.S. Pat. No. 5,672,538) note that the vertical edges of field oxide, formed by LOCOS and projecting above the silicon surface, can be rather steep and thus likely to degrade the integrity of metal lines subsequently deposited over it. Their patent teaches how this edge may be rendered less steep.
Mathews (U.S. Pat. No. 5,393,694) describes a problem similar to that solved by the present invention but provides a different solution. The groove is over-filled with polysilicon, then planarized, and then steam oxidized to convert it to silicon oxide so that the trench becomes uniformly filled with silicon oxide and the groove, in effect, disappears. Tsai et al. (U.S. Pat. No. 5,712,185) use silicon nitride as part of a shallow isolation trench formation process. This silicon nitride is no longer present after the final structure has been formed.